For Companies

Joint research, contract research, academic consulting and lectures

Our lab works end to end, from integrated circuits (FPGA, ASIC, SRAM compute-in-memory) and edge AI to real-time robot control (imitation learning, acceleration of Vision-Language-Action models, low-latency bilateral control).

We are happy to discuss these topics with companies.

What we work on

See Research for details.

Design automation

AI for Circuits
  • Prototype flows that generate Verilog and layout (GDSII) from specifications or natural language
  • Feasibility studies of introducing LLMs into an existing design flow
  • Validation on open PDKs and FPGAs

AI hardware

Circuits for AI
  • Estimating and implementing speed, power and area of an AI model on FPGA/ASIC
  • Applying our design assets: SRAM compute-in-memory macros measured on 22 nm silicon, a multiplication-free DNN accelerator
  • Selecting and benchmarking AI chips and FPGAs

Robot control

Systems & Robotics
  • Retrofitting low-latency control (FPGA-based bilateral control, imitation learning) to existing robots
  • Running and accelerating Vision-Language-Action models on edge devices
  • Real-robot validation of teleoperation and imitation learning

Scope

  • Silicon tape-out is costly and slow; we start with FPGA and simulation-based evaluation
  • We do not do product development itself (mass-production design, maintenance); the work needs a research component
  • The lab has no GPU cluster or large measurement facilities; if these are required, let us talk about how to proceed

How we collaborate

  1. Joint research
  2. Contract research (problem solving first; deliverable is a report; publication is optional)
  3. Academic consulting (selecting and evaluating AI chips and FPGAs, introducing design automation, robot control)
  4. Lectures and corporate training (e.g., “Introduction to AI Chips: Hardware Acceleration for Machine Learning”)

Selected results

  • SRAM compute-in-memory macros measured on 22 nm silicon (IEEE TVLSI 2026, ICCAD 2026)
  • Multiplication-free all-digital DNN accelerator (DAC 2025)
  • Low-latency bilateral control on FPGA and accelerated motion generation for Vision-Language-Action models (RSJ 2026)
  • Uncertainty-aware haptic shared control for humanoid teleoperation (IEEE RA-L 2023)
  • Low-latency spiking-neural-network inference applied to robot imitation learning (Scientific Reports 2026)

See Publications for the full list.

Contact

If any of this sounds relevant, feel free to get in touch — an exploratory conversation is perfectly fine. We can also talk under an NDA.

  • Laboratory: pj.u-ayogan ta onawa

  • Nagoya University collaboration office: inquiry form