Publications

International Journals

2026

  1. TCBBIO
    Biologically Constrained DNA Encoding with Triplet Networks for Similarity Image Retrieval
    Takefumi Koike, Hiromitsu Awano, and Takashi Sato
    IEEE Transactions on Computational Biology and Bioinformatics, 2026

2025

  1. IEEE Access
    Beamforming Feedback-Based Respiration and Heart Rate Estimation Toward Firmware-Agnostic WiFi Sensing
    T. Kanda, S. Kondo, H. Shimomura, and 3 more authors
    IEEE Access, 2025
  2. IEICE
    Analog In-Memory Computing from a Memory-Agnostic Perspective: Theory, Nonidealities, and Hardware-Aware Training
    Yusuke Sakemi, Hiromitsu Awano, and Takashi Morie
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2025
  3. TCAD
    Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir
    Sosei Ikeda, Hiromitsu Awano, and Takashi Sato
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025

2024

  1. OJCAS
    Double MAC on a Cell: A 22-nm 8T-SRAM based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline
    Hiroto Tagata, Takashi Sato, and Hiromitsu Awano
    IEEE Open Journal of Circuits and Systems, 2024
  2. TECS
    A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits
    Dehua Liang, Hiromitsu Awano, Noriyuki Miura, and 1 more author
    ACM Transactions on Embedded Computing Systems, Sep 2024
  3. Front. Neurosci.
    BayesianSpikeFusion: Accelerating Spiking Neural Network Inference via Bayesian Fusion of Early Prediction
    Takehiro Habara, Takashi Sato, and Hiromitsu Awano
    Frontiers in Neuroscience, Aug 2024
  4. OJCAS
    StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification
    Dehua Liang, Jun Shiomi, Noriyuki Miura, and 1 more author
    IEEE Open Journal of Circuits and Systems, May 2024

2023

  1. RA-L
    Uncertainty-aware Haptic Shared Control with Humanoid Robots for Flexible Object Manipulation
    Takumi Hara, Takashi Sato, Tetsuya Ogata, and 1 more author
    IEEE Robotics and Automation Letters, Oct 2023
  2. TECS
    Modular DFR: Digital delayed feedback reservoir model for enhancing design flexibility
    Sosei Ikeda, Hiromitsu Awano, and Takashi Sato
    ACM Transactions on Embedded Computing Systems, Oct 2023
  3. IEEE Access
    Pay Attention via Quantization: Enhancing Explainability of Neural Networks via Quantized Activation
    Yuma Tashiro and Hiromitsu Awano
    IEEE Access, Apr 2023
  4. Integration
    B2N2: Resource Efficient Bayesian Neural Network Accelerator Using Bernoulli Sampler on FPGA
    Hiromitsu Awano and Masanori Hashimoto
    Integration, Mar 2023

2022

  1. TCAD
    Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification
    Sosei Ikeda, Hiromitsu Awano, and Takashi Sato
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov 2022
  2. IEICE
    BayesianPUFNet: Training Sample Efficient Modeling Attack for Physically Unclonable Functions
    Hiromitsu Awano and Makoto Ikeda
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Oct 2022
  3. IEICE
    A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter
    Dehua Liang, Jun Shiomi, Noriyuki Miura, and 2 more authors
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jul 2022
  4. IEICE
    Temporal Ensemble SSDLite: Exploiting Temporal Correlation in Video for Accurate Object Detection
    Lukas Nakamura and Hiromitsu Awano
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jul 2022

2021

  1. J. Comp. Physiol.
    Visualization of chorus structure in multiple frog species by a sound discrimination device
    Hiromitsu Awano, Masahiro Shirasaka, Takeshi Mizumoto, and 2 more authors
    Journal of Comparative Physiology A, 2021

2020

  1. Integration
    Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge–Response pair acquisition using Built-In Self-Test before shipping
    Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, and 4 more authors
    Integration, Mar 2020

2019

  1. IEICE
    An ASIC Crypto Processor for 254-bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field
    Hiromitsu Awano, Tadayuki Ichihashi, and Makoto Ikeda
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jan 2019

2018

  1. IEICE
    Low Latency 256-bit Fp ECDSA Signature Generation Crypto Processor
    Shotaro Sugiyama, Hiromitsu Awano, and Makoto Ikeda
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec 2018

2017

  1. Sci. Rep.
    Visualizing Phonotactic Behavior of Female Frogs in Darkness
    Ikkyu Aihara, Phillip Bishop, Michel Ohmer, and 5 more authors
    Scientific Reports, 2017
  2. IEICE
    Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation
    Hiromitsu Awano and Takashi Sato
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec 2017
  3. TVLSI
    RTN in Scaled Transistors for On-chip Random Seed Generation
    Abinash Mohanty, Ketul Sutaria, Hiromitsu Awano, and 2 more authors
    IEEE Transactions on Very Large Scale Integration Systems, Aug 2017
  4. TVLSI
    Scalable Device Array for Statistical Characterization of BTI-Related Parameters
    Hiromitsu Awano, Shumpei Morita, and Takashi Sato
    IEEE Transactions on Very Large Scale Integration Systems, Apr 2017
  5. JRM
    A Swarm of Sound-to-Light Conversion Devices for Monitoring Acoustic Communication among Small Nocturnal Animals
    Takeshi Mizumoto, Ikkyu Aihara, Takuma Otsuka, and 2 more authors
    Journal of Robotics and Mechatronics, Feb 2017

2016

  1. IEICE
    Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter based Importance Sampling
    Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jul 2016

2014

  1. IEICE
    Automation of Model Parameter Estimation for Random Telegraph Noise
    Hirofumi Shimizu, Hiromitsu Awano, Masayuki Hiromoto, and 1 more author
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec 2014
  2. TDMR
    BTIarray: A Time-overlapping Transistor Array for Efficient Statistical Characterization of Bias Temperature Instability
    Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato
    IEEE Transactions on Device and Materials Reliability, Sep 2014
  3. Sci. Rep.
    Spatio-Temporal Dynamics in Collective Frog Choruses Examined by Mathematical Modeling and Field Observation
    Ikkyu Aihara, Takeshi Mizumoto, Takuma Otsuka, and 4 more authors
    Scientific Reports, Jan 2014

2013

  1. TED
    Compact Modeling of Statistical BTI Under Trapping/detrapping
    Jyothi Bhaskarr Velamala, Ketul B. Sutaria, Hirofumi Shimizu, and 4 more authors
    IEEE Transactions on Electron Devices, Nov 2013

2012

  1. IEICE
    Bayesian Estimation of Multi-trap RTN Parameters using Markov Chain Monte Carlo Method
    Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and 1 more author
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec 2012

International Conferences

2025

  1. VLSI
    A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics
    Quan Cheng, Qiufeng Li, Zhengke Yang, and 10 more authors
    In Digest of Symposium on VLSI Technology and Circuits, 2025
    to appear
  2. DAC
    Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation
    Hiroto Tagata, Takashi Sato, and Hiromitsu Awano
    In Design Automation Conference, 2025
    accepted
  3. DAC
    Weighted Range-Constrained Ising-Model Decoder for Quantum Error Correction
    Xinyi Guo, Hiromitsu Awano, and Takashi Sato
    In Design Automation Conference, 2025
    accepted
  4. CICC
    A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing
    Q. Cheng, Q. Li, W. Dong, and 9 more authors
    In Proceedings of IEEE Custom Integrated Circuits Conference, 2025
    to appear
  5. ASP-DAC
    Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K
    Takuma Kawakami, Takashi Sato, and Hiromitsu Awano
    In Asia and South Pacific Design Automation Conference, Jan 2025

2024

  1. ICCD
    S3M: Static Semi-Segmented Multipliers for Energy-efficient DNN Inference Accelerators
    Mingtao Zhang, Quan Cheng, Hiromitsu Awano, and 2 more authors
    In IEEE International Conference on Computer Design, Nov 2024
  2. DAC
    Triplet network-based DNA encoding for enhanced similarity image retrieval
    Takefumi Koike, Hiromitsu Awano, and Takashi Sato
    In Design Automation Conference, Jun 2024

2023

  1. DATE
    Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent
    Sosei Ikeda, Hiromitsu Awano, and Takashi Sato
    In Design, Automation, and Test in Europe, Mar 2023
  2. ICMTS
    Introducing Transfer Learning Framework on Device Modeling by Machine Learning
    Kota Niiyama, Hiromitsu Awano, and Takashi Sato
    In International Conference on Microelectronic Test Structure, 2023
  3. ASP-DAC
    DependableHD: A Hyperdimensional Learning Framework for Edge-oriented Voltage-scaled Circuits
    Dehua Liang, Hiromitsu Awano, Noriyuki Miura, and 1 more author
    In Asia and South Pacific Design Automation Conference, Jan 2023

2022

  1. ISCAS
    Pay Attention via Binarization: Enhancing Explainability of Neural Networks via Binarization of Activation
    Yuma Tashiro and Hiromitsu Awano
    In IEEE International Symposium on Circuits and Systems, May 2022
  2. ASP-DAC
    DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification
    Dehua Liang, Jun Shiomi, Noriyuki Miura, and 1 more author
    In Asia and South Pacific Design Automation Conference, Jan 2022
    Best Paper Candidate

2021

  1. IROS
    Binary Neural Network in Robotic Manipulation: Flexible Object Manipulation for Humanoid Robot Using Partially Binarized Auto-Encoder on FPGA
    Satoshi Ohara, Tetsuya Ogata, and Hiromitsu Awano
    In International Conference on Intelligent Robots and Systems, 2021
    Best RoboCup Paper Award Candidate
  2. DATE
    BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter
    Dehua Liang, Masanori Hashimoto, and Hiromitsu Awano
    In Design, Automation, and Test in Europe, Feb 2021

2020

  1. DATE
    BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA
    Hiromitsu Awano and Masanori Hashimoto
    In Design, Automation, and Test in Europe, Mar 2020
    Oral, acceptance rate 26%

2019

  1. ISCAS
    PUFNet: a Deep Neural Network Based Modeling Attack for Physically Unclonable Function
    Hiromitsu Awano, Tomoki Iizuka, and Makoto Ikeda
    In IEEE International Symposium on Circuits and Systems, May 2019
  2. DATE
    FourQ on ASIC: Breaking Speed Records for Elliptic Curve Scalar Multiplication
    Hiromitsu Awano and Makoto Ikeda
    In Design, Automation, and Test in Europe, Mar 2019
    Long presentation, acceptance rate 24%

2018

  1. ASSCC
    31.3us/Signature-Generation 256-bit Fp ECDSA Cryptoprocessor
    Shotaro Sugiyama, Hiromitsu Awano, and Makoto Ikeda
    In Asian Solid-State Circuits Conference, Nov 2018
  2. ASSCC
    An Encryption-Authentication Unified A/D Conversion Scheme for IoT Sensor Node
    Vinod V. Gadde, Hiromitsu Awano, and Makoto Ikeda
    In Asian Solid-State Circuits Conference, Nov 2018
  3. ATC
    ASIC Coprocessor for 254-bit Prime-Field Pairing based on General Purpose Arithmetic Unit on Quadratic Extension Field
    Hiromitsu Awano and Makoto Ikeda
    In International Conference on Advanced Technologies for Communications, Oct 2018
  4. DATE
    Ising-PUF: A Machine Learning Attack Resistant PUF Featuring Lattice Like Arrangement of Arbiter-PUFs
    Hiromitsu Awano and Takashi Sato
    In Design, Automation, and Test in Europe, Mar 2018
    Oral, acceptance rate 23.7%

2017

  1. ATS
    Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip Connection
    Keitaro Koga, Hiromitsu Awano, and Makoto Ikeda
    In Asian Test Symposium, Nov 2017
  2. ASP-DAC
    Efficient Circuit Failure Probability Calculation along Product Lifetime Considering Device Aging
    Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato
    In Asia and South Pacific Design Automation Conference, Jan 2017
    Acceptance rate 31%

2016

  1. DAC
    Efficient Transistor-level Timing Yield Estimation via Line Sampling
    Hiromitsu Awano and Takashi Sato
    In Design Automation Conference, Jun 2016
    Acceptance rate 22.6%
  2. GLSVLSI
    Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation
    Song Bian, Michihiro Shintani, Shumpei Morita, and 3 more authors
    In Great Lakes Symposium on VLSI, May 2016
  3. ISCAS
    Physically Unclonable Function Using RTN-Induced Delay Fluctuation in Ring Oscillators
    Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, and 1 more author
    In IEEE International Symposium on Circuits and Systems, May 2016
  4. TAU
    Efficient Transistor-level Timing Yield Estimation via Line Sampling
    Hiromitsu Awano and Takashi Sato
    In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Mar 2016

2015

  1. VMC
    Fast Monte Carlo for Timing Yield Estimation via Line Sampling
    Hiromitsu Awano and Takashi Sato
    In Workshop on Variability Modeling and Characterization, Nov 2015
  2. DATE
    ECRIPSE: An Efficient Method for Calculating RTN-Induced Failure Probability of an SRAM Cell
    Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato
    In Design, Automation, and Test in Europe, Mar 2015
    Oral, acceptance rate 22.4%
  3. AAAI-W
    Recognition of In-field Frog Chorusing using Bayesian Nonparametric Microphone Array Processing
    Yoshiaki Bando, Takuma Otsuka, Ikkyu Aihara, and 4 more authors
    In AAAI Workshop on Computational Sustainability, Jan 2015

2014

  1. ICSICT
    A Scalable Device Array for Statistical Device-Aging Characterization (invited)
    Takashi Sato, Hiromitsu Awano, and Masayuki Hiromoto
    In IEEE International Conference on Solid-State and Integrated Circuit Technology, Oct 2014
  2. ESSDERC
    Variability in Device Degradations: Statistical Observation of NBTI for 3996 Transistors
    Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato
    In European Solid-State Device Research Conference, Sep 2014

2013

  1. VMC
    Statistical Observation of NBTI and PBTI Degradations
    Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato
    In Workshop on Variability Modeling and Characterization, Nov 2013
  2. ISQED
    Multi-trap RTN Parameter Extraction based on Bayesian Inference
    Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and 1 more author
    In International Symposium on Quality Electrical Design, Mar 2013

2012

  1. CICC
    Statistical Aging Under Dynamic Voltage Scaling: a Logarithmic Model Approach
    Jyothi Bhaskarr Velamala, Ketul B. Sutaria, Hirofumi Shimizu, and 3 more authors
    In IEEE Custom Integrated Circuits Conference, Sep 2012
  2. ISQED
    Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices
    Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, and 2 more authors
    In International Symposium on Quality Electrical Design, Mar 2012

2011

  1. ICONIP
    Use of a Sparse Structure to Improve Learning Performance of Recurrent Neural Networks
    Hiromitsu Awano, Shun Nishide, Hiroaki Arie, and 3 more authors
    In International Conference on Neural Information Processing, Nov 2011

2010

  1. SMC
    Human-Robot Cooperation in Arrangement of Objects Using Confidence Measure of Neuro-dynamical Systems
    Hiromitsu Awano, Tetsuya Ogata, Shun Nishide, and 3 more authors
    In International Conference on Systems, Man, and Cybernetics, Jun 2010

Invited Talks

2025

  1. AIチップ入門:機械学習のためのハードウェアアクセラレーション
    皓光 粟野
    May 2025

2020

  1. ベイジアン深層ニューラルネットのハードウェアアクセラレーション
    皓光 粟野
    Aug 2020
  2. Security Evaluation of Physically Unclonable Function in Deep Learning Era
    Hiromitsu Awano
    Jan 2020

2019

  1. Physically Unclonable Functionとモデリング攻撃
    皓光 粟野
    Dec 2019
  2. オープンソース機械学習ライブラリを用いたPUFに対するモデリング攻撃
    皓光 粟野
    Mar 2019

2017

  1. Line samplingを用いたモンテカルロ法に基づくタイミング歩留り解析の高速化
    皓光 粟野 and 高史 佐藤
    Mar 2017
  2. モンテカルロ法と集積回路設計の接点
    皓光 粟野
    Mar 2017

Domestic Conferences

2024

  1. ニューロモーフィックチップAkidaにおける高電力効率な推論のためのゼロアウェアなSNN学習法
    丈博 羽原, 高史 佐藤, and 皓光 粟野
    In 情報処理学会DAシンポジウム2024, Aug 2024
  2. 誤り耐性量子コンピュータの実現に向けた表面符号デコーダの極低温CMOS集積回路による実装検討
    若泰 王, 高史 佐藤, and 皓光 粟野
    In 情報処理学会DAシンポジウム2024, Aug 2024
  3. 4.2Kでの65nmバルクpMOSトランジスタにおけるランダムテレグラフノイズの評価
    拓真 川上, 高史 佐藤, and 皓光 粟野
    In 情報処理学会DAシンポジウム2024, Aug 2024
  4. エッジデバイス実装を指向したロボット遠隔操作時のハプティックガイダンス生成法の検討
    拓己 原, 高史 佐藤, and 皓光 粟野
    In ロボティクス・メカトロニクス講演会2024, 2024
  5. ダイナミック比較器とLookup Tableを用いた乗算不要な機械学習向けインメモリアクセラレータ
    寛斗 田形, 高史 佐藤, and 皓光 粟野
    In LSIとシステムワークショップ2024, May 2024

2023

  1. リーク電流で演算する量子化ニューラルネットワーク向け低電力SRAMインメモリアクセラレータ
    寛斗 田形, 高史 佐藤, and 皓光 粟野
    In 情報処理学会DAシンポジウム2023, Aug 2023
  2. ヘブ則に基づく動的重み調整手法を利用したスパイキングニューラルネットワークの低レイテンシ・低消費エネルギ推論
    丈博 羽原, 高史 佐藤, and 皓光 粟野
    In 情報処理学会DAシンポジウム2023, Aug 2023

2022

  1. 適応的閾値制御に基づくスパイキングニューラルネットワークの推論エネルギー削減
    丈博 羽原, 高史 佐藤, and 皓光 粟野
    In 情報処理学会DAシンポジウム2022, Sep 2022
  2. 8T-SRAMを用いた同時2入力対応な2値化ニューラルネットワーク用インメモリアクセラレータ
    寛斗 田形, 高史 佐藤, and 皓光 粟野
    In 情報処理学会DAシンポジウム2022, Sep 2022
  3. 離散化アテンションによる説明可能な自動操舵システム
    悠馬 田代 and 皓光 粟野
    In 情報処理学会DAシンポジウム2022, Sep 2022
  4. スパイキングニューラルネットワークの高速低エネルギー推論に向けた動的閾値調整手法
    丈博 羽原 and 皓光 粟野
    In 電子情報通信学会VLD設計技術研究会, Mar 2022
  5. 8T-SRAMを用いた高スループットな2値化ニューラルネットワーク用インメモリアクセラレータ
    寛斗 田形 and 皓光 粟野
    In 電子情報通信学会VLD設計技術研究会, Mar 2022
  6. 遠隔ロボットによる円滑な柔軟物操作のための力触覚ガイドつき制御システム
    智子 飯田 and 皓光 粟野
    In 電子情報通信学会VLD設計技術研究会, Mar 2022

2021

  1. FPGA実装を指向した部分2値化オートエンコーダに基づく人型ロボットによる柔軟物操作システム
    慧 大原, 哲也 尾形, and 皓光 粟野
    In 情報処理学会DAシンポジウム2021, Sep 2021
  2. MOSFETリザバーと線形出力層を用いた短時間学習
    寛也 村田, 祐貴 久米, 松 辺, and 2 more authors
    In 情報処理学会DAシンポジウム2021, Sep 2021
  3. ビット重要度の違いに着目した符号アテンションによる説明能力向上
    悠馬 田代 and 皓光 粟野
    In 情報処理学会DAシンポジウム2021, Sep 2021
  4. ベイジアンフュージョンによるスパイキングニューラルネットワークの低エネルギ推論
    勇統 赤木 and 皓光 粟野
    In 情報処理学会DAシンポジウム2021, Sep 2021

2020

  1. 2値化オートエンコーダを用いたヒューマノイドロボットによる柔軟物操作のための軽量End-to-End学習
    慧 大原, 哲也 尾形, and 皓光 粟野
    In 情報処理学会第82回全国大会, Mar 2020

2019

  1. 高位設計フローにベイズ最適化法を応用した設計空間探索
    亮平 中山, 皓光 粟野, and 誠 池田
    In 電子情報通信学会ハードウェアセキュリティ研究会, Jul 2019
  2. 深層学習を利用したPUFに対する攻撃耐性の評価
    皓光 粟野, 知希 飯塚, and 誠 池田
    In 電子情報通信学会総合大会企画セッション, Mar 2019
  3. PUFを用いた個体識別システムにおける機械学習攻撃に対する脆弱性の評価
    知希 飯塚, 泰弘 小笠原, 敏宏 片下, and 3 more authors
    In 電子情報通信学会ハードウェアセキュリティ研究会, Mar 2019
  4. Micciancio-Walterアルゴリズムを用いた高速なガウシアンサンプラーの設計
    啓太郎 古賀, 皓光 粟野, and 誠 池田
    In 電子情報通信学会ハードウェアセキュリティ研究会, Mar 2019

2018

  1. 超高速な楕円曲線暗号の実現に向けたFourQのASIC実装
    皓光 粟野 and 誠 池田
    In LSIとシステムワークショップ, May 2018
  2. 65nmプロセスを用いたOptimal Ateペアリング向け12次拡大体演算器の評価
    忠之 市橋, 皓光 粟野, and 誠 池田
    In 電子情報通信学会ハードウェアセキュリティ研究会, Mar 2018
  3. 楕円曲線デジタル署名アルゴリズムの高速ハードウェア設計
    昇太郎 杉山, 皓光 粟野, and 誠 池田
    In 電子情報通信学会ハードウェアセキュリティ研究会, Mar 2018
  4. 深層ニューラルネットワークを用いたDouble-Arbiter PUFに対するモデリング攻撃
    知希 飯塚, 皓光 粟野, and 誠 池田
    In 電子情報通信学会VLD設計技術研究会, Mar 2018
  5. 2次拡大体上の汎用演算器を用いた254bit素数ペアリング向けASICコプロセッサ
    皓光 粟野, 忠之 市橋, and 誠 池田
    In 暗号と情報セキュリティシンポジウム, Jan 2018
  6. ツイストしたエドワーズ曲線上のスカラー倍算のハードウェア実装
    昇太郎 杉山, 皓光 粟野, and 誠 池田
    In 暗号と情報セキュリティシンポジウム, Jan 2018

2017

  1. BN曲線上におけるOptimal Ateペアリング向け演算ハードウェアの最適化
    忠之 市橋, 皓光 粟野, and 誠 池田
    In 電子情報通信学会技術報告会(デザインガイア2017), Nov 2017
  2. チャレンジヒステリシス特性を有するPUFの設計とシミュレーションに基づく性能評価
    皓光 粟野 and 高史 佐藤
    In 情報処理学会DAシンポジウム2017, Sep 2017

2016

  1. 信号確率伝播に基づいたプロセッサのためのNBTI起因最大遅延パスの抽出
    松 辺, 道広 新谷, 俊平 森田, and 3 more authors
    In 第29回回路とシステムワークショップ, May 2016

2015

  1. モンテカルロ法に基づくタイミング歩留り解析の高速化
    皓光 粟野 and 高史 佐藤
    In 電子情報通信学会技術報告会(デザインガイア2015), Nov 2015
  2. デバイス特性の経年劣化に起因する不良確率変化の効率的な解析手法
    皓光 粟野, 正之 廣本, and 高史 佐藤
    In 情報処理学会DAシンポジウム2015, Aug 2015
  3. 視聴覚統合NMFによるカエル合唱音声の分析
    克寿 糸山, 宜昭 坂東, 皓光 粟野, and 2 more authors
    In 情報処理学会研究報告 音楽情報科学, May 2015
  4. RTN起因のリングオシレータ発振周波数変動を利用したPUF
    幹 吉永, 皓光 粟野, 正之 廣本, and 1 more author
    In 電子情報通信学会VLSI設計技術研究会, Mar 2015
  5. NBTIによる閾値電圧変化の確率的モデル化に関する一考察
    雅紘 佐藤, 翔一 飯塚, 皓光 粟野, and 2 more authors
    In 電子情報通信学会総合大会, Mar 2015

2014

  1. RTNを考慮したSRAM不良確率の高速計算
    皓光 粟野, 正之 廣本, and 高史 佐藤
    In 電子情報通信学会技術研究報告(デザインガイア2014), Nov 2014
  2. 3996トランジスタにおけるNBTI劣化の統計的ばらつき
    皓光 粟野, 正之 廣本, and 高史 佐藤
    In 情報処理学会DAシンポジウム2014, Aug 2014
  3. ランダムテレグラフノイズを用いたチップ識別手法の一検討
    幹 吉永, 皓光 粟野, 正之 廣本, and 1 more author
    In 電子情報通信学会ソサイエティ大会, Sep 2014
  4. 振動子モデルと音声可視化システムを用いたアマガエルの合唱法則の解析
    一究 合原, 皓光 粟野, 武志 水本, and 4 more authors
    In 第39回AIチャレンジ研究会,人工知能学会, Mar 2014

2013

  1. トランジスタアレイを用いたBTI劣化の統計的観測
    皓光 粟野 and 高史 佐藤
    In 情報処理学会DAシンポジウム2013, Aug 2013

2012

  1. 情報量規準を用いるRTNモデルパラメータ推定の自動化
    裕史 清水, 皓光 粟野, 弘 筒井, and 2 more authors
    In 情報処理学会DAシンポジウム2012, Aug 2012

2011

  1. ランダムテレグラフノイズモデル化のためのパラメータ推定法の検討
    皓光 粟野, 裕史 清水, 弘 筒井, and 2 more authors
    In 電子情報通信学会技術研究報告(デザインガイア2011), Nov 2011
  2. 再帰結合神経回路モデルへのスパース構造導入による学習能力の向上
    皓光 粟野, 哲也 尾形, 淳 谷, and 2 more authors
    In 情報処理学会第73回全国大会, Mar 2011

2010

  1. 確信度を用いた物体配置作業における人間ロボット協調
    皓光 粟野, 哲也 尾形, 徹 高橋, and 2 more authors
    In 日本ロボット学会第28回学術講演会, Sep 2010
  2. RNNを用いた行為予測による人間とロボットの協調物体配置
    皓光 粟野, 哲也 尾形, 徹 高橋, and 2 more authors
    In 情報処理学会第72回全国大会, Mar 2010